Dual SD/SDIO Host controller device /CG200V2

The CG200V2 is a SD/SDIO host controller which is fully compliant with current and next generation high-speed SD memory specifications. In supporting dual SD hosts, the CG200V2 is able to accommodate both SD memory and SDIO cards and can simplify applications that require multiple cards (Example: IEEE802.11g Wireless LAN and SD memory.) The CG200V2 control register set is compliant with the SD Host Controller Standard Specification Ver.1.00.

In addition, the CG200V2 supports various host interfaces such as IDE, PCI and Generic 8/16/32 bit CPU bus interface. The CG200V2fs unique dual SD slots and various CPU interfaces provide for flexible system architecture design.

In IDE-SD Bridge mode with IDE interface, data can be transmitted using Ultra DMA mode3 (Ultra ATA/44). When used together with high-speed SD memory, maximum throughput reaches 22.5MByte/sec. The CG200V2 allows direct access to SD memory using the PCfs standard IDE interface without additional drivers, which enables it to work with SD memory on PC systems simply with the OS provided IDE driver.


Specifications

Latest SD Specification
   Applicable PHYSICAL LAYER Specification Ver.2.00
   SD Host Controller Standard Specification Ver.1.00
   Support SD Specification Ver.2.0 (high-speed SD memory applicable)
   Support high-speed memory (Max. SD Clock: 50MHz)
   Support high-capacity SD memory(SDHC) on PCI, CPU bus mode.

Dual SD Slots
   Support high-speed SD memory
     Maximum throughput 22.5MByte/sec(at SD Clock:50MHz)
   Support SDIO commands.

Flexibility in Operation Modes
   IDE-SD Bridge bus mode
     Support Ultra-DMA mode3 (Ultra ATA/44)
   PCI bus mode:Build-in PCI Ver.2.3 interface (32bit/33MHz)
   Generic 8/16/32bit bus mode for embedded applications
   Low power design by efferent clock management.

Ultra small package
   144pin VFBGA (8.0 x 8.0 x 1.0mm)
   Pin pitch 0.5mm

CG200V2 Evaluation board/CG200 V2EDK
CG200V2EDK is an evaluation kit for CG200V2, equipped with two SD slots, PCI connector, IDE header and a generic 8/16/32bit CPU bus interface. It is simple to adapt to customerfs own system and facilitate software development and system evaluation.